Joint Test Action Group (JTAG) is the common name for what was later standardized as the IEEE 1149.1, “Standard Test Access Port and Boundary-Scan Architecture”, where IEEE is short for the Institute of Electrical and Electronics Engineers. An IEEE 1149.7 standard is a complementary standard to IEEE 1149.1, adding additional functionality. JTAG was initially devised for testing printed circuit boards using boundary scan and is still widely used for this application.
The “boundary scan architecture” of IEEE 1149 uses a 5-pin serial protocol for setting and reading the values on pins without directly accessing the core logic. A serial scan path known as a boundary scan register (BSR) intercepts signals between the core logic and the pins. When the system is not in test mode, the boundary scan register connects the signals of the core logic to the pins transparently. In test mode, the BSR may be used to set and/or read values. In external mode, the values set or read will be the values of the I/O pads, also known as ‘pins’. In internal mode, the values set or read will be the values of the core logic.
The BSR is a shift register, which forms a path around the core logic. Signal pins of the core logic of a system being tested are connected to cells that make up the BSR, with these cells surrounding the core logic (boundary). The shift register is connected to the input and exit of test equipment, allowing test vectors to be sent to the BSR, thus testing the core logic.
Despite this standardized approach, because the system under test is in a “test mode”, some real-time scenarios are not tested using the boundary scan architecture.
Thus, there is a continuing need for a mechanism for performing real-time testing of core logic that overcomes the shortcomings of the prior art.